Ultra thin fet

ABSTRACT

Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts while the wafer bulk is intact. The top surface is then contacted by a rigid wafer carrier and the bulk wafer is then ground/etched to an etch stop layer at the bottom of the thin wafer. A thick bottom contact is then applied to the bottom surface and the top wafer carrier is removed. All three contacts of a MOSFET may be formed on the top surface in one embodiment or defined by the patterning of the bottom metal contact.

RELATED APPLICATION

This application is based on and claims the benefit of U.S. ProvisionalApplication Ser. No. 60/715,356, filed on Sep. 8, 2005, entitled FOILFET, to which a claim of priority is hereby made and the disclosure ofwhich is incorporated by reference.

FIELD OF THE INVENTION

This invention relates to MOSgated devices and more specifically relatesto a low voltage MOSFET in which the substrate is almost completelyeliminated.

BACKGROUND OF THE INVENTION

MOSgated devices such as MOSFETs, IGBTs and the like are well known.Vertical conduction MOSgated devices are usually formed in a relativelythick wafer or die, which may have a thickness of several hundredmicrons. A thin top junction receiving layer which may be only about 3μthick (for low voltage devices) is located on the top surface of thewafer. Conduction in such devices, when the device is on, is from asource electrode on the top surface to a drain electrode on the bottomsurface. The resistance R_(DSON) through the thick wafer substrate addsto the device on resistance.

It is desired to reduce this on resistance R_(DSON) and it is known tothin the wafers to about 60 microns for this purpose. The resultingdevice is mechanically fragile and hard to handle.

It would be desirable to even more drastically thin the wafer whilestill providing sufficient mechanical strength so that the wafer and thedie singulated therefrom can be easily handled during fabrication andpackaging.

BRIEF DESCRIPTION OF THE INVENTION

In accordance with the invention, a wafer is thinned to the thickness ofa thin foil, for example, to 3 microns for a 25 volt device, and couldbe thinned within the range of 1 micron to 10 microns.

The top surface of the foil has a relatively massive copper electrodes(20 microns thick, for example), and the bottom of the wafer may alsohave a similar massive (20 microns, for example) bottom electrodes tolend mechanical rigidity to the silicon foil.

Vias may extend through the thin foil of silicon to bring top contactsto the bottom of the foil as desired.

In one embodiment of the invention, one or both of the source and gateelectrodes wrap around the chip edge to be available at either sidethereof

A novel process for producing this result is also disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a small segment of a wafer prepared in accordance with theinvention, and particularly shows a single die position on the wafer.

FIG. 2 shows the wafer of FIG. 1 after the formation of device junctions(not shown) and the device electrodes.

FIG. 3 shows the wafer of FIG. 2 after a gold flash coating of thesource, drain and gate electrodes, all on the top surface of thewafer/die.

FIG. 4 shows the application of a wafer carrier mount to the device topsurface and the subsequent removal of the bulk portion of the wafer.

FIG. 5 shows the device of FIG. 4 in which a rigid conductive back plateis fixed to the bottom of the wafer, and the wafer carrier mount isremoved.

FIGS. 4A and 4B illustrate an alternative method according to thepresent invention.

FIG. 6 shows the starting wafer made in accordance with a secondembodiment of the invention.

FIG. 7 shows the wafer of FIG. 6 after the formation of junctions for aplurality of die and shows two full die widths.

FIG. 8 shows the wafer of FIG. 7 after the application of a front coversupport plate (or wafer carrier mount).

FIG. 9 shows the wafer of FIG. 8 after the removal of the N+ bulkmaterial and P etch stop and a subsequent photolithography step to formopenings between adjacent die in the wafer.

FIG. 10 shows the wafer of FIG. 9 after the deposition of a back contactwhich enters the photolithographically formed openings in the streetareas of the wafer.

FIG. 11 shows the wafer of FIG. 10 after the removal of the wafercarrier mount.

FIGS. 12, 13 and 14 shows three formats for die singulated from thewafer of FIG. 11, depending on the finishing etch of the back copper.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a starting wafer 10 which has a thick (e.g., 300 to 550micron) N⁺ bulk region 11 containing a P type diffused etch stop region12 and an N⁺ drain diffusion region 13. An N⁻ epitaxially grown layer 14is formed atop the N⁺ layer 13. The thickness of the N⁺ layer 13 and theN⁻ epitaxial layer 14 defines a very thin layer, or foil, about 1 to 10microns thick, depending on the breakdown voltage needed. For a 25 voltdevice, for example, the thickness would be about 3 microns.

The desired implants and diffusions are then carried out to form thedesired FET junction pattern in the N⁻ epi layer 14. The top surface ofthe device is passivated as by passivation layer 20 (FIG. 2). Anydesired passivation is used, such as TEOS, PECVD oxides, HDP oxides,SACVD oxide, PSG, BPSG, Si₃ N₄ etc. If a top drain contact is desired onthe same surface as the gate and source electrodes, a via opening 30,filled with copper 31, or the like may be formed.

A thin copper seed layer 40 (FIG. 2) is then formed over the full uppersurface of the wafer (FIG. 2) and a photo-resist layer 41 is depositedatop the seed layer 40 and is patterned to form contact for electrodeson the silicon. A thick metal plate, for example, copper which may be 20microns thick, is then deposited into the area exposed by openings inthe photoresist (FIG. 2) as by any desired plating or depositionprocess, defining contacts 50, 51, 52 which may be drain, gate andsource contacts respectively.

Thereafter, as shown in FIG. 3, the photoresist 41 is striped, theexposed copper seed 40 is striped and a gold flash 60 (or other preciousmetal) is applied to the massive copper contacts 50, 51, 52 forsolderability.

As next shown in FIG. 4, a soft or hard wafer carrier 60 is adhered tothe top surface of the wafer and the N⁺ substrate 11 is ground back andthen etched away to the P type etch stop 12. Note that the wafer may besingulated where the P etch stop layer is interrupted 12′.

During the above process, the wafer strength is derived from the wafercarrier mount 60 and the wafer 10 is easily handled in conventionalwafer fabrication equipment.

The P type etch stop layer 12 is then removed (FIG. 5) and oxides areremoved from any vias formed during the etch back process.

Thereafter, as shown in FIG. 5, an electroless backside contact 15(about 20 microns thick) is formed on the N⁺ layer 13, completing theprocessed wafer.

Alternatively, some interruptions 12′ can be provided and used as viasto make electrical connection between back side contact 15 and a frontside (for example, drain contact) 50. Referring to FIGS. 4A and 4B, aninterruption 12′ is provided preferably under the location of frontdrain contact 50, and then filled with metal when back side contact 15is formed as shown by FIG. 5A. Note that as a result etching a via fromthe front and filling the same with copper or the like material isobviated.

Note that back side contact 15 can be formed by a variety of methodsincluding electroless titanium, nickel, copper, or gold plating,sputtering a seed layer and electroplating of the desired metal,sputtering or evaporating the desired metal.

The wafer carrier mount 60 is then removed. Note that all electrodes areavailable for connection at the top of the wafer.

FIGS. 6 to 11 show a second embodiment of the invention. Thus, in FIG.6, the starting wafer 100 is like that of FIG. 1 except that the etchstop layer 102 is continuous across the wafer. Thus, the wafer 100consists of a thick N⁺ bulk 101, the P type etch stop layer 102, and athin N⁺ drain diffusion layer 103. The N⁻ epitaxially grown layer 104 isformed atop N⁺ region 103.

A suitable set of implants and diffusions are formed in the N⁻ epi layer104 to form the desired FET or other device. The thickness of layers 103and 104 may be about 1 to 10 microns and are non-self supporting in theabsence of the N⁺ bulk 101.

Thereafter, and as shown in FIG. 7, source and gate contacts are formed,shown for several adjacent die, as source contacts 110, 111, 112 andgate contacts 114, 115 (for the die with source contacts 110, 111respectively). The contacts may be plated and etched in streets 120,121.

As next shown in FIG. 8, a thick, rigid front cover support plate 130(like the wafer carrier mount 60 of FIG. 4) is removably adhered to thesurface defined by tops of the front contacts 110 to 114 and the N⁺ bulkregion 101 is removed by a grind/etch step, back to the etch stop layer102. The wafer carrier 60 provides the necessary strength for the waferafter bulk 104 is removed.

Thereafter and as shown in FIG. 9, the P type etch stop layer 102 isremoved (or converted to the N type) and a photoresist 140 is applied tothe back layer and is opened at windows 141, 142, 143 which define theperipheries of adjacent die. The exposed silicon layers 103 and 104 arethen etched, as shown in FIG. 9, in a street pattern.

Copper 150 is then plated or otherwise applied to the back surface andinto the openings in the streets defined by windows 141, 142, 143. Athick copper mass, for example, 10 to 20 microns thick, is left on thebottom surface of the wafer. Note that the copper 150 within the streetscontacts the source and gate metals on the top surface as shown in FIG.10.

Copper 150 is then etched from the backside of the wafer foil asdesired, depending on the final device desired.

Thereafter, the backside is mounted to a suitable carrier and the frontcarrier 130 is removed. Metal 150 which is preferably copper, but can beany suitable conductor, has sufficient strength to allow the subsequenthandling of the wafer and the die diced therefrom.

The die which are formed and singulated at streets 120, 121 can have thestructures, for example, of FIGS. 12, 13 or 14, depending on the etch ofthe back contact 150 in FIG. 11.

Thus, the die can have the traditional geometry of FIG. 12, with source110 and gate 113 contacts on the top surface and the thick metal drain150 on the bottom surface.

Alternatively, the die may have the structure of FIG. 13 in which theback contact is separated at area 160 and the gate contact 113 isextended to the bottom surface of the die through metal 150 in thestreet which is retained for this purpose.

A very useful geometry is that shown in FIG. 14 in which two separations170, 171 are formed in the bottom metal 150, with portions of metal 150extending around the edge of the silicon die 103, 104 and contactingsource 110 and gate 113 respectively. This then presents the source,drain and gate electrode on the bottom surface of the die, forsimplified die mounting on a support surface.

Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein.

1. The process of manufacture of a semiconductor device having a diethickness less than about 10 micrometers; said process comprisingforming an etch stop layer in the top surface of a wafer having athickness greater than about 300 micrometers; forming a thin junctionreceiving layer of semiconductor material of thickness less than about10 microns atop said etch stop layer; forming a junction pattern in saidthin junction receiving layer and forming spaced coplanar contacts atopsaid thin junction receiving layer; removably attaching a wafer carriermount to said top surface of said thin junction receiving layer;removing the bulk of said wafer from its bottom surface to said etchstop layer with said wafer carrier providing sufficient strength to saidthin layer to permit its handling without breakage; metallizing theexposed bottom surface of said wafer with a conductive layer ofsufficient thickness and strength to allow handling of said thin layerwithout damage; and thereafter removing said removable wafer carriermount.
 2. The process of claim 1, wherein said thin junction receivinglayer includes a layer of epitaxially deposited silicon.
 3. The processof claim 1, wherein said wafer is N type monocrystalline silicon, andwherein said thin junction receiving layer comprises a thin N⁺ driftregion and an N⁻ epitaxially deposited layer atop said N⁺ drift region.4. The process of claim 1, wherein said step of removing said bulk ofsaid wafer includes a grind step and final etch step to said etch stoplayer.
 5. The process of claim 2, wherein said step of removing saidbulk of said wafer includes a grind step and final etch step to saidetch stop layer.
 6. The process of claim 3, wherein said step ofremoving said bulk of said wafer includes a grind step and final etchstep to said etch stop layer.
 7. The process of claim 1, wherein saidconductive layer is copper and has a thickness greater than about 10micrometers.
 8. The process of claim 2, wherein said conductive layer iscopper and has a thickness greater than about 10 micrometers.
 9. Theprocess of claim 3, wherein said conductive layer is copper and has athickness greater than about 10 micrometers.
 10. The process of claim 4,wherein said conductive layer is copper and has a thickness greater thanabout 10 micrometers.
 11. The process of claim 6, wherein saidconductive layer is copper and has a thickness greater than about 10micrometers.
 12. The process of claim 1, which further includes the stepof forming a via through said thin junction receiving layer and fillingsaid via with a conductive material to connect at least one of saidcontacts on the top surface of said thin junction receiving layer tosaid conductive layer on said exposed bottom surface of said wafer. 13.The process of claim 3, which further includes the step of forming a viathrough said thin junction receiving layer and filling said via with aconductive material to connect at least one of said contacts on the topsurface of said thin junction receiving layer to said conductive layeron said exposed bottom surface of said wafer.
 14. The process of claim4, which further includes the step of forming a via through said thinjunction receiving layer and filling said via with a conductive materialto connect at least one of said contacts on the top surface of said thinjunction receiving layer to said conductive layer on said exposed bottomsurface of said wafer.
 15. The process of claim 7, which furtherincludes the step of forming a via through said thin junction receivinglayer and filling said via with a conductive material to connect atleast one of said contacts on the top surface of said thin junctionreceiving layer to said conductive layer on said exposed bottom surfaceof said wafer.
 16. The process of claim 1, which includes the furtherstep of forming street openings between die positions in said thinjunction receiving layer, and filling said street openings withconductive material to connect at least one of said contacts on the topsurface of said thin junction receiving layer to said conductive layeron said exposed bottom surface of said layer, and opening a window insaid conductive layer to isolate a portion thereof from said materialconnected to said top surface contact, whereby at least two contacts foreach die are connectable at the bottom surface of said die.
 17. Theprocess of claim 3, which includes the further step of forming streetopenings between die positions in said thin junction receiving layer,and filling said street openings with conductive material to connect atleast one of said contacts on the top surface of said thin junctionreceiving layer to said conductive layer on said exposed bottom surfaceof said layer, and opening a window in said conductive layer to isolatea portion thereof from said material connected to said top surfacecontact, whereby at least two contacts for each die are connectable atthe bottom surface of said die.
 18. The process of claim 4, whichincludes the further step of forming street openings between diepositions in said thin junction receiving layer, and filling said streetopenings with conductive material to connect at least one of saidcontacts on the top surface of said thin junction receiving layer tosaid conductive layer on said exposed bottom surface of said layer, andopening a window in said conductive layer to isolate a portion thereoffrom said material connected to said top surface contact, whereby atleast two contacts for each die are connectable at the bottom surface ofsaid die.
 19. The process of claim 7, which includes the further step offorming street openings between die positions in said thin junctionreceiving layer, and filling said street openings with conductivematerial to connect at least one of said contacts on the top surface ofsaid thin junction receiving layer to said conductive layer on saidexposed bottom surface of said layer, and opening a window in saidconductive layer to isolate a portion thereof from said materialconnected to said top surface contact, whereby at least two contacts foreach die are connectable at the bottom surface of said die.